?
IP CORE Search:
 
 
 

eNews Registration
* Name:
* Phone:
*Company Name:
*Country:
* Email:
To Unsubscribe: Send an email to kal@kaltech.co.il with "Remove" at the subject. Thank You.

Customers Log-In

Send page to a friend
* Email:

News

Latest Articles:

Hebrew Article: Agreements and Commercial Contracts in ASIA

Hebrew Article: The Internet and social Media in China

Hebrew Article: AI: Intelligent Technology

Hebrew Article: The Future of Employees Management

Hebrew Article: China Mega Trends

Concept Engineering Adds JavaScript-based Web Capabilities to Nlview at DAC 2016

Hebrew Article: Investment from China

Hebrew Article: Hong Kong Vs. Singapore - Zero-sum Game

Hebrew Article: Where to open a Business Development office in China and APAC

Hebrew Article: Sales Team Training in APAC

Hebrew Article: Building Sales Team in APAC

Hebrew Article: Languages @ Marketing in APAC

Hebrew Article: New Opportunity in China

China: Personal Opp ortunity Vs. Business Opportunity English Hebrew


KAL eNews History:

SimXACT Gate Level Simulation Tool

IP Review: D32PRO & the mysteries of 32-bit IP Cores

KAL and Avery Design Systems Inc signed representation agreement for functional verification IP core

Try the best Memory CTRL IP CORE by Eureka USA

IP Review – LCD 32 Controller

IP Review - DF CAN

IP Review – USB2 w/ ULPI interface

32bit PCI IP Core Update

NEW IP core: 32bit CPU by DCD

Concept Engineering Presents Ver 6 of All Debugging Tools for Analog, Digital, AMS and SoC Designers 2015

New UART IP Core by DCD

Concept Engineering Introduces S-engineTM: Automatic System-Level Schematic Generation Capabilities Combined with IP Editing and Assembly

New IP Core for ASIC/FPGA: EEPROM IP Core with configurable SPI

New IP Core for ASIC/FPGA: ADPCM

New IP Core for ASIC/FPGA: LCD Controller IP Core

New IP Core for ASIC & FPGA: Smart Card Reader

New IP Core for ASIC/FPGA: HDLC/SDLC

SPEF Parasitic Netlist Interface to SpiceVision® PRO and StarVision® PRO

Programmable Interrupt Controller D8259 from Digital Core Design

LIN IP Core for ASIC/FPGA compatible with LIN 1.3, 2.1 and the newest 2.2.

DT8051 - the world's most powerful tiny 8051 IP core for ASIC/FPGA

Debugging Tools for IC, SoC and FPGA Designers

RF Layout course - Ireland on 23-26 October 2012

First time 8051 CPU (IP Core for ASIC/FPGA) 66 times faster!

What to Look for When Selecting 3rd-Party IP

Concept Engineering Adds Support for Cadence® Virtuoso® Spectre® to StarVision™ PRO, SpiceVision® PRO and SGvision™ PRO

New customer for StarVisionPro - TowerJazz

Success story: Yitran Communications

The World’s fastest 8051 IP core

CAN IP Core for Automotive Applications

New Oscillator Option for syn1588® NICs Development Board

syn1588® NIC Development Boards: Twice the Accuracy

Concept Engineering Introduces Integrated Debugging Tool for Mixed-signal Design at DAC 2011

White Paper - Understanding SD, SDIO and MMC Interface By Eureka Technology

Quad-Pipelined Ultra High Performance 8051 IP core for ASIC/FPGA

April 26th 2011 - RF Layout Training Dublin Ireland

Best wishes to our EDA tools partner Concept Engineer for 20 year birthday

Development Board for SD or MMC

White Paper: The Fundamentals of Using NAND Flash Devices in System Design

Fully customizable memory controller IP Core by Eureka Technologies

NEW EDA tool by Concept Engineering: Spice 2 OpenAccess

ASIC EDA Tools Update July 2010

Eureka Technology Supports PLB Bus Interface for Most of Its Popular IP Cores

The syn1588® board product family by Oregano Systems will release in Q1/2010 a new version of NICs driver and stack.

Flash/ROM/SRAM Controller IP Core by Eureka Technologies Inc - Short Overview

Using the World’s Smallest SYN1588® Fully Integrated Clock Synchronization Solution as a Building Block for a Radically New Approach to Coordinated Test, Debug, Trace and Replay in Distributed Systems

Concept Engineering and SDS exhibit at DAC 2009

KAL & ICMASK offers IC Layout Courses locally

DCD's smallest and fastest DT8051 CPU IP Core

High Performance DDR3 SDRAM Controller by Eureka Technology

Take a look at our 0.18um, 0.13um and 90-45nm Service!

Development Board for SD or MMC System Development

8051 Processor IP Core By Digital Core Design

SYN1588 Clock IP Core By Oregano Systems

New SD/SDIO/MMC Slave Controller IP Core by Eureka Technologies

News:

July 2017: KAL and Avery Design Systems Inc signed representation agreement for functional verification IP core

May 2016: KAL and Comport Data Inc signed representation agreement for analog and mixed signal ASIC service for Medical and industrial applications

June 2013: KAL and Creative Chips GmbH signed representation agreement for turnkey solution ASIC Service for analog / mixed signal application for the Middle East customers and Asia Pacific

17th March, 2010 - IEEE1588 Technology Day, Herzeliya, Israel

January 2009 - KAL and MAZ to provide Open-Book Business model for Analog and Mixed Signal ASIC Projects - Hebrew press

January 2009 - KAL host the 2009 ASIC Technology Symposium a long with MAZ, Concept Engineering and PREMA Semiconductor

November 2008 - KAL to singe an exclusive representative agreement with IC Mask Design - A leading provider for IC Training and design services.

January 2008 - KAL have lunched a new web site design.

April 2007 - Using SiGe VS. CMOS Technology - Hebrew Article

March 2007 - IC Nexus and KAL Bring 90nm and Finer Nodes
ASIC Services to Israeli Market ג€“ more

June 2006 - Using and verifying an open source processor in a 100% first time right commercial ASIC - Hebrew Article

February 2006 - Requirement and Possibilities for Industrial Sensor Interface Application by Stephan Klesy / PREMA Semiconductor GmbH - Hebrew Article

September 2005 - KAL to singe an exclusive representative agreement with Eureka Technology Inc. - A leading provider for ASIC IP (Intellectual Property) Cores.

May 2005 - IP (Intellectual Property) On time On budget - Hebrew Article

April 2005 - KAL has launched sticker campaign to promote ASIC design- Get the Sticker

March 2005 - GateVisionֲ® graphical analyzer for Netlist gate level visualization, timing and bug analysis- Hebrew Article

December 2004 - SpiceVisionֲ® graphical analyzer for Spice circuits and models - Hebrew Article

May 2004 - KAL to singe an exclusive representative agreement with Concept Engineering GmbH - A leading provider for visualization tools for ASIC and FPGA development.


 
Copyright © 2016 - KAL Katav Associates Silicon Technologies - All Rights Reserve.