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IP Core
KAL's IP List

The combination of leading ASIC/FPGA knowledge and customer ASIC project that we have done and doing in present, leading us to look for and to partnered with the leading IP vendors. Our Vendors offering leading IP for SOC (System-On-Chip) design for high speed performance, low power demand and small foot print.

Available Analog & Digital IP Cores:

Verification IP
IP Name Description
PCIe VIP .
NVMe/NVMf VIP .
eMMC/eMMC HC VIP .
DDR 2/3/4/5 VIP .
LPDDR 2/3/4 VIP .
HDMI VIP .
CAN/CAN FD VIP .
I2C VIP .
UniPro VIP .
M-PHY VIP .

CPU Cores
IP Name Description
8 bit - PIC Processor Pipelined High Performance Microcontroller Family
8 bit- HC68HC11 8-bit FAST Microcontrollers Family
8 bit - 8051 Pipelined High Performance Speed Optimized Microcontrollers family
8 bit - Quad-Pipelined 8051 Revolutionary Quad-Pipelined Ultra High Performance 8-bit Microcontroller
8 Bit - 80251 56 times faster than 80C51 and has 50% more efficient code space utilization, comparing to classic 8051
8 bit - Z80 8-Bit Microprocessor
16/32 bit - D68000 16/32-bit CISC Microprocessor
16 bit - MSP430 TI's compatible MSP430
32 bit ARM (as part of ASIC design) ARM 9xx, ARM11xx (part of an ASIC design)
32 bit - D32PRO royalty-free, universal and fully configurable CPU,


Peripherals
IP Name Description
ADPCM ADPCM Code Modulation
EEPROM SPI Ctr -
Smart Card Reader ISO 7816-3/EMV4.2
LCD Controller 24-bit RGB output and synchronization
HDLC/SDLC 8-bit, 16-bit, 32-bit CPU interface
Floating Point Unit Floating Point Arithmetic Unit
I2C Master/Slave I2C Bus Interface ג€“ Master/Slave
SPI Master/Slave Serial Peripheral Interface ג€“ Master/Slave
CAN bus Configurable CAN Bus Controller
Programmable Peripheral Interface Programmable Peripheral Interface
UART/ UART with FIFO Configurable UART/ with FIFO
PWM Pulse Wide Modulator 
Timer 8254 Programmable Interval Timer 
Programmable Timer Programmable Interval Timer
Interrupt Controller Programmable Interrupt Controller
Ethernet Controller 10/100/1000 BaseT Programmable Peripheral Interface
Gigabit Ethernet MAC DMAC in cooperation with external PHY device enables network functionality in design. It is capable of transmitting and receiving Ethernet frames to and from the network
PCMCIA/ CompactFlash Host Adapter Supports all four access types as defined in the PC Card/PCMCIA/Compact Flash standards.  
PCMCIA/ CompactFlash Slave Controller This module interface with the PCMCIA card signals on one side and a user interface on this other side 
DMA Controller Designed for direct data transfer independent of CPU operations.
SDIO/SD Memory/MMC Host/Slave Controller A host controller for SD memory card, SDIO and MMC interface. The core connects the host CPU of the system to the SD card socket. External SD cards can be accessed by the host CPU through the controller core IP.
Smart Card Interface  
SATA Host Serial ATA Host with AHB/PCIe/AXIג„¢ interfaces
SATA Device Serial ATA Device with AHB/PCIe/AXIג„¢ interfaces
IDE ATA IDE Controller IP Core
IEEE 1588 Slave/Master/ Programmable IEEE1588 Standard's Precision Time Protocol (PTP)


Memory Controllers
IP Name Description
Mem Connect Comprehensive, Customizable, and Silicon Proven IP Solution for memory system design.
SDRAM Controller Interface between multiple SDRAM memory storage and a processor or DMA device.
DDR/DDR2/DDR3 SDRAM Controller IP core that interface between multiple DDR SDRAM devices and a memory requestor such as a processor or DMA device.
NAND Flash Controller Provides an easy interface for user to access NAND Flash devices.
Flash/EEPROM/SRAM Controller Allows two or more access ports to share memory access to the FLASH, ROM and SRAM devices
CompactFlash Host/Slave controller Complaint to Compact Flash specification and PC card/PCMCIA
CompactFlash with EXCA registers Complaint to Compact Flash specification and PC card/PCMCIA. Additions register set similar to 82365SL.


USB Controllers and IPs
IP Name Description
USB 2.0 Host/Device
(i/f certified)
USB 2.0 Device Controller with AHB/PCI/Generic bus interface and UTMI+/ULPI interface
USB 3.0 Host/Device USB 3.0 Host or Device Controller with AHB/PCI/Generic bus interface


MIPS CPU Interface
IP Name Description
MIPS - SysAD Bus Slave This module interfaces between the MIPS CPU on SysAD bus to system and I/O resources
MIPS - SysAD Bus to PCI Host bridge This controller allows the MIPS CPU to initialize and access all PCI devices
MIPS - EC interface to SDRAM Controller This controller provides high speed SDRAM data access to the MIPS CPU and user-defined logic
MIPS - EC Interface to PCI Host Bridge This controller allows the MIPS CPU core to initialize and access all PCI devices
MIPS - EC Interface Bus Slave This module interfaces between the MIPS CPU on EC interface to system and I/O resources.


AHB Bus interfaces
IP Name Description
AHB Bus Master Initiate data transaction on the AHB bus master. Allowed user-defined logic such as DMA or peripheral bus controllers to access system resources on the AMBA AHB bus
AHB Bus Slave AHB bus slave is designed to interface between multiple user-defined logics to the ARM CPU on the AMBA AHB bus.
AHB to SDRAM Controller This controller provides high speed SDRAM data access to the ARM CPU and user-defined logic.
AHB to DDR SDRAM Controller This controller provides high speed DDR SDRAM data access to the ARM CPU and user-defined logic.
AHB to PCI Host Bridge This controller allows the ARM CPU to initialize and access all PCI devices.
AHB DMA Controller This DMA controller is designed to operate directly on the AMBA AHB bus.


Analog IP Cores
IP Name Description
Sigma Delta ADC 14 Bit, 1 KS/s, 0.18µm, 2nd Order Modulator @4MHz
Sigma Delta ADC 12 Bit, 12 KS/s, 0.18µm, 2-1 MASH Modulator @12MHz
Sigma Delta ADC 12/14 Bit, 10 MS/s, 0.18µm, 2-1 MASH Modulator @64MHz @ 8KHz Bandwidth or 500KHz Bandwidth
Sigma Delta ADC 10 Bit, 250 KS/s, 0.18µm, 1st Order Modulator @32MHz
SAR ADC 12 Bit, 1 MS/s, 0.18µm, C based
SAR ADC 10 Bit, 1 MS/s, 0.18µm, R based
Sigma Delta ADC 13 Bit, 1 MS/s, 0.18µm, 2-1-1 MASH Modulator @64MHz @ 500KHz Bandwidth
RDAC 8 Bit, 5 MS/s
RDAC 10 Bit, 1 MS/s, 0.18µm
Sigma Delta DAC 12 Bit, 1 MS/s, 0.13µm
Others Please Contact Us


PCI Bus Controllers and Peripherals
IP Name Description
PCI Express Functions as an interface to the PCI Express transceiver for a PCI Express Endpoint/Root Port/Dual Mode/Switch Port. AHB/AXIג„¢ interface
PCI-X Host Bridge, Master/Target 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode.
PCI Host Bridge, Target,
Master/Target
32-bit PCI host bridge IP is designed for interfacing the host CPU with the PCI bus.
PCI-PCI Bridge 32-bit PCI-to-PCI bridge is designed for interfacing between the primary PCI bus and the secondary PCI buses.
PCI-ISA Bridge IP core that provides bridging capability between the PCI bus and the ISA bus.
PCI Bus Arbiter performs bus arbitration among multiple masters on the PCI bus


PowerPC CPU Interface
IP Name Description
Power PC Bus Master The PowerPC bus master is a bus interface unit designed for the PowerPC host bus
PowerPC to PCI Host bridge The PowerPC to PCI bridge is designed for interfacing the PowerPC CPU with the PCI bus
PowerPC Bus Arbiter provides all the necessary functions to arbitrate multiple bus masters directly connected to the PowerPC host bus
PowerPC Bus Slave Bus interface unit designed for the PowerPC host bus. It is designed to work on any 60x compliant bus architecture


 
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