Our IP portfolio includes CAN, CANFD, Multi CAN, Lin and FlexRay IP cores. Today we would like to review the CANFD IP core, premium IP core.

CAN/CANFD IP Review – Silvaco

 

The CAN Controller is a synthesizable IP block providing Controller Area Network (CAN) functionality compliant with the CAN Specification Revision 2.0 Part B. Proven in high-volume standard devices, the CAN Controller features a programmable bit rate to support applications that require a high-speed (up to 1 Mbit/s) or a low-speed CAN interface. Fifteen message buffers, each configurable for transmit or receive, and programmable acceptance filtering provide support for both Full-CAN and BasicCAN operation.

The host interface of the CAN Controller complies with the AMBA 2 APB protocol. Host-accessible control registers provide CPU control of bit rate, diagnostic functions, enabling/disabling the CAN Controller, CAN pin logic level, CAN bit time partitioning, incoming message filtering, transmit message prioritization, and enabling/ disabling interrupts. Status registers provide CAN node, interrupt, and error/diagnostic status.

The CAN bus interface consists of serial transmit and receive signals that connect to an external transceiver through chip-level I/O pads. To reduce chip-level pin count, the transmit and receive signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.

Features:

  • Programmable bit rate—up to 1 Mbit/sec
  • Standard or extended frames
  • 15 message buffers—each configurable for transmit or receive
  • Remote frame support
  • Automatic transmission after reception of a Remote Transmission Request (RTR)
  • Automatic receive after transmission of an RTR
  • Programmable acceptance filtering
  • Global mask for message buffers 0–13
  • Individual mask for message buffer 14 Programmable transmit priority
  • Time stamp counter—programmable for automatic reset on transmit/receive
  • Interrupt capabilities • Interrupts available for message buffer transmit/receive and CAN error conditions
  • Interrupts can be individually enabled/disabled
  • Diagnostic functions
  • Error identification
  • Loopback (internal or external)
  • Listen-only mode for initialization

Gate Count and Performance:

Gate count and maximum frequency depend on synthesis tool and target technology. Example values for a typical 130-nm technology are:

  • 5500 (NAND2 equivalent) gates
  • 100 MHz (APB clock)

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