by Graham Bell Silvaco
In the creation of an ASIC or SoC a wide variety of digital components are needed. Standard logic cells are used to implement the high-level description of the chip which is typically written in RTL. A synthesis tool such as Design Compiler or RTL Compiler is used to generate a gate-level netlist built out of the standard logic cells from a cell library. Communication on and off of the chip, requires unique input/output cells or I/Os that can drive off-chip wiring and withstand electrostatic discharges in the range of thousands of volts. The other main category is digital memories typically SRAMS that can take up a significant amount of area on the die for a chip. These 3 categories of digital design IP are called Foundation IP.
Silvaco offers a complete portfolio of SIPware Foundation IP for the creation of ASICs and SoCs for almost any process node. For over 20 years, the Nangate team, now a part of Silvaco, have been providing Foundation IP to the design community. They pride themselves in offering the best-in-class components with a full set of services which is a one-stop shop for chip developers and foundries.
Standard Cell Library Foundation IP
Today’s foundries offer a wide variety of process nodes ranging in size from 250nm, and above, down to 7nm and below. Process nodes of 110nm, and above, are considered mature since they have been in the market for over 20 years.
The standard cell libraries that were developed earlier at that time do not include recent technology developments. Here is a list of how standard cells and process offerings have changed over this time:
- Tapless architecture
- Clock gating
- Vt variants.
- Power management kits (PMK) & multi-power islands
- Multi-bit FFs
- Fine grain sizing
- Complex function matching
This means that legacy libraries can be further improved for power footprint, performance and area.
With 700 – 1,200 standard cells and multi VTs and track heights, the Silvaco standard library offers thousands of cell variants, enabling applications from ultra-low power to high-speed. Silvaco carefully sizes each cell family in the library, optimizing transistor sizes, P/N ratios and drive strength granularity for further power and performance gains. Silvaco’s EDA platform for Layout Optimization, Cello, enables a new level of optimization, with 35% area and 20% power reduction compared to off-the-shelf libraries from other vendors. Multi-bit and multi-height standard cells boost routing density even further by reducing pin count and packing more functionality inside standard cells. For instance the detailed review and exploration of 180nm design rules by Silvaco engineers resulted in the creation of a cell architecture that achieves a raw gate density of 162K gates per square millimeter.
The Silvaco library is extended with a Power Management Kit, taking power reduction to the next level with features such as multi-voltage design and power gating. Libraries are characterized for multiple PVT corners with extended voltage range and are compatible with multiple foundries.
To use a Silvaco Foundation library in your next project, you can contact Silvaco or you can request it from your Foundry. Many foundries already have our optimized library even if they are not listed.