eNews: Jivaro – Parasites Reduction and more

 

Jivaro is a solution dedicated to the reduction of parasitic networks. It helps backend physical verification teams
(SPICE or FastSpice users) speeding up post layout simulation of huge parasitic extracted circuits, while keeping a very high accuracy.

Jivaro applies an ingenious mathematical approach to perform Model Order Reduction (MOR). Contrary to
any heuristic technology, Jivaro allows to trade-off between accuracy and reduction with the user
controlling the benefits. Jivaro can be applied with different thresholds on different parts of the design to
maximize reduction. It can also offer more than MOR through the reduction of the number of active devices.

Jivaro has been proven to dramatically accelerate IC simulation while preserving an outstanding accuracy
and has been adopted at leading IDM companies and fabless worldwide for technology nodes at 130nm and
below. Jivaro was added to TSMC’s Custom Reference Flow flow starting with 28nm.

Jivaro is known to be used for designs at technology nodes of 10nm.

Features:
• All types of parasitic netlist components: R, RC, RCC, RLC, RLCK, controlled sources
• Supports the following I/O formats: DSPF, SPEF, SPICE3, HSPICE, SPECTRE, CalibreView, reads and writes OpenAccess databases
• Supports temperature-dependent parasitic networks
• Can be applied differently on selected nets or sub-circuits withinthe hierarchy. Selection of the different nets can be along a path
• Compatible with all major EDA tools
• Additional capabilities for path-based reduction
• Multi-finger reduction
• Supports negative resistors

Options:

• Multi-threading
• Support of inductance and mutual inductance
• Seamless integration within the Cadence Virtuoso® platform
(several possibilities)
• Graphical User Interfaces to pilot the reduction options
• Inline binaries for batch runs

 
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