eNews: MIL-STD-1553 IP core Overview

 

BMC IP is available for customers who want to implement the 1553 interface inside their system.

The IP can be linked to any FPGA device. It can beconfigured with single or multiple channels andprotocols.

BMC advanced MIL-STD-1553 IP core come with a set of enhanced capabilities allowing for your
communication bus to have real time digital wiring fault detection and prognosis, so your aircraft will
experience minimum downtime.

The cores are suitable for any MIL-STD1553 application, including direct replacement ofexisting ICs.
It includes multiple receive/transmit buffers for 1553 applications, sub-address filtering, error bit detection and/or injection, programmable
conditions for RT status error bit, Long LOOP Test error and many others.

There are a variety of ARINC protocols but the mostcommon is ARINC 429/575/572/582/615.., a 32 bit
data protocol. It has a two wire line with true and complement data. The electrical signals use a NRZI format.
Some equipment requires a parity bit in the bit stream (odd or even), others do not. BMC-IP has
implemented all these conditions.

There also a number of ARINC protocols with 6 wires; 3 signals twisted pair, like ARINC 561, ARINC
571 and ARINC 581. The electrical signals use a NRZ format. BMC-IP supports these protocols as well.

The ARINCs receive/transmit IP interface is based on a 32 cache FIFO each with 32 bit words to protecxt
the system from data overlap.

ARINC 453/708 software operates exactly as ARINC 2-6 wires protocols.

ARINC 573/717 has programmable transmit/receive rate; 64/128/256/512 words (10 bits) p/second and
error injection as well. It channel is independently configurable through software and operates according
to Harvard biphase protocol.

The BMC ARINC-IP offers UNLIMITED independent transmitters and independent receivers in the
same core.

BMC can customize the IP according to customer requirements.

 

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